3D Nanoelectronic Computer Architecture and Implementation by D. Crawley, K. Nikolic, M. Forshaw

By D. Crawley, K. Nikolic, M. Forshaw

It really is turning into more and more transparent that the two-dimensional format of units on computing device chips is commencing to prevent the improvement of high-performance desktops. three-d constructions could be had to give you the functionality required to enforce computationally in depth initiatives. three-D Nanoelectronic computing device structure and Implementation experiences the cutting-edge in nanoelectronic equipment layout and fabrication and discusses the architectural elements of three-D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. it is a worthy reference for these eager about the layout and improvement of nanoelectronic units and know-how.

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5 Experimental setup For completeness, we include here a short description of the experimental setup that was used for measuring the properties of the molecular wires. 17(a) shows a picture of the test rig; on the right-hand side can be seen the arm for manipulating the chip, whilst on the left is a microscope used for visualizing the alignment of the chips. 17(b) shows a close-up of the rig and shows the configuration of electrical connections onto the chip. The CORTEX test chips were deliberately designed to be as simple as possible, with the sole aim of providing the partners with a series of chips with electrode pads (either aluminium or gold).

7. Diamond has a thermal conductivity of 2000 W m−1 K−1 whilst silicon has a thermal conductivity of 150 W m−1 K−1 . The authors constructed a stack using test chips which included heaters and diodes for temperature sensing. The system was air cooled. Compared to other work, the layers used in this stack were quite thick—200 µm for the silicon and 300 µm for the diamond. Using this technique, the authors claim that a power dissipation of between 80 and 100 W could be achieved with a cubic volume of about 16 cm3 (at a peak temperature of around 73 ◦C).

In practice, since both PE1 and PE2 are identical, PE2 would also generate a signal in the event of it detecting a fault on its outputs but this signal could only be used to indicate a system failure. There is no means of generating a correct result in the same processor cycle if both PE1 and PE2 detect faults on their outputs at the same time. 12—for simplicity, the modifications needed in order to access the memory on the two layers as a contiguous block are not shown. 12. Processing Element modified for fault-tolerant operation.

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