An ASIC Low Power Primer: Analysis, Techniques and by Rakesh Chadha

By Rakesh Chadha

This booklet presents a useful primer at the recommendations used in the layout of low energy electronic semiconductor units. Readers will enjoy the hands-on strategy which begins shape the ground-up, explaining with simple examples what strength is, the way it is measured and the way it affects at the layout means of application-specific built-in circuits (ASICs). The authors use either the Unified strength structure (UPF) and customary energy layout (CPF) to explain intimately the facility purpose for an ASIC after which advisor readers via a number of architectural and implementation concepts that would support meet the facility cause. From reading procedure energy intake, to concepts that may be hired in a low strength layout, to a close description of 2 trade criteria for shooting the ability directives at numerous levels of the layout, this booklet is stuffed with info that may supply ASIC designers a aggressive side in low-power design.

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Extra resources for An ASIC Low Power Primer: Analysis, Techniques and Specification

Example text

5 0 fer is output low, the DC current flows from the termination voltage supply VTT through the transmission line into the PAD pin of the output buffer to ground supply. Assume an IO with an Rout of 34 ohm,3 and a 66 ohm termination impedance at destination. 1. 913mW (with 66ohm termination to VDDQ/2) Note that the above computation is for power dissipated within the IO buffer; there is additional power (supplied by VDDQ of the IO buffer) which is dissipated in the 66 ohm termination resistor. 2.

Each of the techniques for reducing the leakage power requires adding other control signals to enable the low power modes. LS”; value : 1622700; } leakage_power () { when : “LS”; value : 777000; } The above example is for a memory macro with one power supply for the core array and the peripheral logic. 2 Power Dissipation in Analog Macros The power dissipation in the analog macros, such as PLLs and SerDes macros, normally cannot be classified into leakage and active power components. For example, these macros may dissipate significant DC power in the voltage-controlled oscillator (VCO) block.

0587” \ ); } } } A similar description is provided for the other input pin also. Note that for combinational cells, the internal power dissipated in the cell when the output does not switch is relatively small in comparison to the scenario when the output of the cell also switches. 2 Active Power in Sequential Cells As seen in the previous section, the switching power can be specified on an input–output pin pair basis (for scenarios where the output pin switches) or as part of the input pin description (for scenarios where the input transition does not result in an output transition).

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