By Marvin Onabajo
This publication describes numerous options to deal with variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The tools provided are effects from contemporary examine works related to receiver front-end circuits, baseband clear out linearization, and information conversion. those circuit-level innovations are defined, with their relationships to rising system-level calibration techniques, to track the performances of analog circuits with electronic tips or regulate. assurance additionally incorporates a technique to make the most of on-chip temperature sensors to degree the sign energy and linearity features of analog/RF circuits, as confirmed by way of try out chip measurements.
- Describes quite a few variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
- Includes integrated trying out strategies, associated with present commercial trends;
- Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch aid approaches;
- Describes theoretical options in addition to experimental effects for try out chips designed with variation-aware techniques.
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Additional info for Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip
1 Background 33 on PVT simulations. 13 lm CMOS technology are provided in Sect. 5, and conclusions are given in Sect. 6. 2 Attenuation-Predistortion Linearization Methodology Signal attenuation at the OTA input  reduces the effective transconductance and decreases the SNR. Alternatively, distortion cancellation by means of cross-coupled differential pairs results in increased power consumption and noise level proportional to the transistor parameters in the additional path. Since the extra differential pair normally has less transconductance than the main pair, the effective transconductance is reduced by 10–50%.
Onabajo, J. Silva-Martinez, F. Fernandez, E. Sánchez-Sinencio, An on-chip loopback block for RF transceiver built-in test. IEEE Trans. Circuits Syst. Express Briefs 56(6), 444–448 (2009) 27. G. Srinivasan, A. Chatterjee, F. Taenzler, Alternate loop-back diagnostic tests for wafer-level diagnosis of modern wireless transceivers using spectral signatures, in Proceedings 24th VLSI Test Symposium, May 2006, pp. 222–227 28. A. Haider, S. Bhattacharya, G. Srinivasan, A. Chatterjee, A system-level alternate test approach for specification test of RF transceivers in loopback mode, in Proceedings of 18th International Conference on VLSI Design, Jan 2005, pp.
These blocks produce digital bitstreams for analysis of fault locations. In general, inclusion of auxiliary circuitry during a loopback test increases the observability of faults, but with the associated trade-offs that have been discussed for on-chip measurement circuitry in Sect. 2. 4 Digital Performance Monitoring with Analog Compensation A BIT approach for complex transceiver chips that has become increasingly popular in recent years is depicted in Fig. 7. It incorporates accurate digital monitoring and I/Q mismatch correction in the baseband processors as well as a few analog observables such as outputs from received signal strength indicators (RSSIs) or DC control voltages of blocks that give some insights into their operating conditions.